This invention relates generally to methods and apparatus for on-chip testing of integrated circuits (xe2x80x9cICsxe2x80x9d) and, more particularly, to a method and apparatus for enabling and disabling access to IC test modes and test functions.
Very large-scale integrated (VLSI) circuit chips manufactured with modem IC technologies routinely include hundreds of thousands of circuit devices (e.g., transistors). As the number of on-chip devices increases, the complexity of circuit permutations increases. To adequately test VLSI chips, built-in test devices commonly reside on the IC substrate with operational circuitry.
Resident test circuits often are accessed via the same chip pins as the operational circuits. To initiate a test operation, a prescribed signal pattern is applied to the chip under test. To avoid inadvertent entry into a test mode, application of a known out-of-spec voltage (e.g., xe2x80x9csuper-voltagexe2x80x9d) to a prescribed pin may be required throughout the test procedure. There is concern, however, with continually applying an out-of-spec voltage. Specifically, applying an out-of-spec voltage for an extended period of time can damage the IC and its internal circuits. Another concern is that leakage specifications for the prescribed pin may not be met. Yet another concern is that the out-of-spec voltage may alter the electrical properties of the IC substrate during the time the voltage is applied. If so, then functional and performance results occurring in a test mode may differ from those in normal operating modes. Another concern is that the out-of-spec voltage level may fall during a test procedure so as to be within specification. This inadvertently terminates the test mode. When simultaneously testing many ICs, uneven power signal distribution will cause such variation of the out-of-spec voltage, terminating the test mode for one or more ICs. Accordingly, there is need for an alternate manner of preventing inadvertent entry into (and out of) a test mode.
According to the invention, a test-mode latching circuit includes disable/re-enable capability. The test-mode latching circuit is part of test circuitry residing on a common IC host with operational circuitry. The test circuitry is accessed to perform test functions on the operational circuitry during a test mode. A test mode for a given test function is entered by latching a test mode identification key into a test-mode latching circuit. In response to the test key, a corresponding test function occurs. For some test functions, the appropriate test key triggers a self-test process. For other test functions, the appropriate test key puts the IC into a specific test mode for receiving and responding to test vectors.
According to one aspect of the invention, the test-mode latching circuit includes an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, a test key is not latched and, thus, test modes are not entered.
According to another aspect of the invention, the test-mode latching circuit includes a disable circuit, a re-enable circuit, control logic and a latch. The latch is for storing the test key. The disable circuit is for triggering a change into the disable state. The re-enable circuit is for triggering a change into the enable state. The control circuit is coupled to the disable circuit, re-enable circuit and latch and defines the state of the latch as disable or enable based signal levels input from the disable circuit and enable circuit.
In one embodiment, the test-mode latching circuit initially is in an enable state. As a result, accessing test modes upon initial fabrication of the IC is a simple process. Upon completion of factory testing, the disable circuit activates a test-key disable signal. The control logic responds to the disable signal to put the test-mode latching circuit in the disable state. Once disabled, test modes cannot be accessed again until the test-mode latching circuit is put into an enable state.
In one embodiment, the disable circuit and/or re-enable circuit include an anti-fuse capacitor. The disable circuit""s capacitor responds to a super-voltage to activate the test-key disable signal. Similarly, the re-enable circuit""s capacitor responds to a super-voltage to activate the test-key re-enable signal. In another embodiment, the disable circuit and/or enable circuit include a programmable logic device (e.g., flash cell) for responding to the super-voltage to activate the test-key disable signal or test-key re-enable signal.
According to another aspect of the invention, the re-enable circuit includes a xe2x80x9csuper-voltagexe2x80x9d detect circuit which detects an out-of-spec voltage having a magnitude above a prescribed threshold level. According to one embodiment of the invention, the super-voltage detect circuit includes a field device. In response to a threshold out-of-spec voltage (xe2x80x9csuper-voltagexe2x80x9d), the field device switches a signal to allow the anti-fuse capacitor or programmable logic device (e.g., flash cell) to activate the test-key re-enable signal. The test-key re-enable signal is active while (i) the detect circuit detects the out-of-spec voltage, and (ii) the re-enable circuit receives an out-of-spec voltage (e.g., the capacitor shorts in response to the out-of-spec voltage, or the programmable logic device triggers a state change in response to the out-of-spec voltage).
An advantage of the field device embodiment is the absence of leakage at the IC pin coupled to the detect circuit. The super-voltage is sufficiently high to prevent unknowing users from accidentally enabling test modes.
According to another aspect of the invention, the out-of-spec voltage need not be maintained at the re-enable circuit to maintain the test-mode latching circuit in the reenable state. Typically, the IC would only be re-enabled at the factory after being returned from a customer. Such a chip is not likely to be re-sold. Thus, a single round of going from the initial enable state to the disable state to the re-enable state is all that is desired for conventional commercial purposes. The anti-fuse capacitor embodiment accomplishes such single round. In the programmable logic device (e.g., flash cell) embodiment, however, the disable and re-enable circuits can be reset to allow additional rounds of disable and re-enable states to be entered. Thus, once re-enabled, the flash cell is reset. The disable circuit then can put the test-mode latching circuit in a disable state and the re-enable circuit can put the test-mode latching circuit back into a re-enable state. The flash cell is reset each time a new round of disable/re-enable states are desired.
According to various embodiments, another signal also occurs before entry into a test mode. A combination of external clock signals occurs to latch a test key into the latch circuit of a host chip. For example, in a dynamic random access memory (DRAM) chip, write enable (WE) and column address strobe (CAS) low signals occur before a row address strobe (RAS) low signal occurs (i.e., a xe2x80x9cWCBRxe2x80x9d sequence). A WCBR sequence occurs to enter into the DRAM host""s WCBR test modes. In embodiments implementing such other signal(s) (e.g., a WCBR sequence), the test-mode latching circuit is initially enabled by the other signal. Once the disable circuit activates the test-key disable signal, the latching circuit stays in the disable state until the re-enable circuit activates the test-key re-enable signal. Once, the test-key re-enable signal is activated, the latching circuit is re-enabled by the other signal (e.g., the WCBR sequence). Initially, and while the test-key re-enable signal is active, the latching circuit may be repeatedly switched between the disable state and reenable state by the other signal (e.g., WCBR sequences).